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high-performance products ?ate 1 www .semtech.com edge6420 per-pin electronics companion dac description features functional block diagram applications revision 4 / april 29, 2002 the edge6420 is a monolithic device which has 64 integrated dacs that are designed specifically for all per channel wide-voltage and current levels needed for pin electronics inside automatic test equipment. the chip can also be used for other applications requiring multiple integrated voltage or current dac outputs. voltage dacs wide voltage (17v range) adjustable full scale range adjustable minimum output 13 bits resolution current dacs ~3.6 ma full scale range adjustable full scale range 6/13 bits resolution the dacs are programmed using a serial interface. the inclusion of 64 total dacs into 1 package offers an extremely high density, flexible solution normally implemented using multiple components. 64 total dacs/package including: wide voltage output range ( 17v range); useful for supervoltage 44 voltage dacs / package 20 current dacs / package adjustable full scale range adjustable output voltage offset small 13x13mm bga package all dacs are guaranteed monotonic test equipment applications requiring multiple programmable voltage and currents ce ck update reset* dac 0 dac 63 vout_ch0_[0:10] iout_ch0_[0:4] channel 0 sdi vout_ch1_[0:10] iout_ch1[0:4] channel 1 vout_ch2_[0:10] iout_ch2_[0:4] channel 2 vout_ch3_[0:10] iout_ch3_[0:4] channel 3 sdo ck_out
2 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 pin description e m a n l l a bn o i t a c o l l l a bn o i t p i r c s e d ] 4 : 0 [ _ ] 3 : 0 [ h c _ t u o v, 2 f , 1 f , 3 g , 5 1 f , 3 1 f , 4 1 f , 5 1 g , 3 1 g , 5 1 k , 3 1 j , 1 k , 3 k , 2 k , 1 j , 3 j , 1 e , 3 f 5 1 l , 3 1 k , 4 1 k . 3 o t 0 s l e n n a h c r o f s e g a l o v t u p t u o c a d a p u o r g ] 6 : 5 [ _ ] 3 : 0 [ h c _ t u o v3 1 l , 4 1 l , 1 l , 2 l , 3 e , 2 e , 5 1 e , 4 1 e . 3 o t 0 s l e n n a h c r o f s e g a t l o v t u p t u o c a d b p u o r g ] 8 : 7 [ _ ] 3 : 0 [ h c _ t u o v4 1 m , 5 1 m , 2 m , 3 l , 2 d , 1 d , 4 1 d , 3 1 e . 3 o t 0 s l e n n a h c r o f s e g q a t l o v t u p t u o c a d c p u o r g ] 0 1 : 9 [ _ ] 3 : 0 [ h c _ t u o v5 1 n , 3 1 m , 3 m , 1 m , 1 c , 3 d , 3 1 d , 5 1 d . 3 o t 0 s l e n n a h c r o f s e g a t l o v t u p t u o c a d d p u o r g ] 1 : 0 [ _ ] 3 : 0 [ h c _ t u o i4 1 n , 5 1 p , 2 n , 1 n , 2 c , 1 b , 4 1 c , 5 1 c . 3 o t 0 s l e n n a h c r o f s e g a t l o v t u p t u o c a d e p u o r g ] 4 : 2 [ _ ] 3 : 0 [ h c _ t u o i, 1 h , 2 h , 2 g , 1 g , 3 h , 4 1 g , 5 1 h , 4 1 h 4 1 j , 5 1 j , 3 1 h , 2 j . 3 o t 0 s l e n n a h c r o f s e g a t l o v t u p t u o c a d f p u o r g r e t s a m _ r5 p t n e r r u c e c n e r e f e r e h t e n i f e d o t d e s u r o t s i s e r l a n r e t x e r e t s a m . s c a d e g a t l o v r o f k c o l b g n i t t e s t e s f f o d n a n i a g e h t r o f ) f , e , d , c , b , a ( _ n i a g _ r9 n , 9 r , 0 1 p , 0 1 n , 0 1 r , 1 1 p e g a t l o v h t o b r o f n i a g t n e r r u c t e s o t r o t s i s e r l a n r e t x e r o f s n i p . s c a d t u p t u o t n e r r u c d n a ) d , c , b , a ( _ t e s f f o _ r5 r , 6 n , 6 p , 6 r p u o r g r o f e g a t l o v t e s f f o e h t t e s o t r o t s i s e r l a n r e t x e r o f s n i p . s ' c a d t u p t u o e g a t l o v d d n a , c , b , a i d s0 1 b. t u p n i a t a d l a i r e s k c1 1 a. r e t s i g e r t f i h s a t a d t u p n i e h t r o f k c o l c e t a d p u6 c. s c a d e h t o t a t a d r e t s i g e r t f i h s e h t r e f s n a r t o t e b o r t s e c0 1 a. e l b a n e p i h c * t e s e r5 c t l u a f e d n w o n k a o t s c a d e h t s t e s . t e s e r p i h c w o l e v i t c a . e t a t s o d s5 b. t u o a t a d l a i r e s t u o _ k c6 a. s e s o p r u p n i a h c y s i a d r o f t u p t u o k c o l c d e t a r e n e g e r t u o _ n a c s1 1 b. n i p t s e t t u p t u o g o l a n a e d o m _ t s e t6 b. n a c s l a n r e t n i r o f n i p e d o m t s e t f e r v9 c. ) p a g d n a b v 5 . 2 a r o f ( t u p n i e c n e r e f e r c c v a2 1 r , 4 n , 2 1 c , 3 c. y l p p u s e g a t l o v g o l a n a e v i t i s o p d d v a7 n , 7 c. y l p p u s v 5 g o l a n a e e v9 p , 9 b , 8 r , 9 a. y l p p u s e g a t l o v g o l a n a e v i t a g e n d n g a8 n , 8 b. ) e s i o n e z i m i n i m ( d n u o r g g o l a n a d n g s7 r , 8 a. d n u o r g y l p p u s d d v d7 p , 7 b. y l p p u s e g a t l o v l a t i g i d d n g d8 p , 8 c. d n u o r g y l p p u s l a t i g i d
3 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 pin description (continued) e m a n l l a bn o i t a c o l l l a bn o i t p i r c s e d c / n, 3 1 a , 2 1 a , 7 a , 5 a , 4 a , 3 a , 2 a , 1 a , 3 1 b , 2 1 b , 4 b , 3 b , 2 b , 5 1 a , 4 1 a , 3 n , 3 1 c , 1 1 c , 0 1 c , 4 c , 5 1 b , 4 1 b , 3 p , 2 p , 1 p , 3 1 n , 2 1 n , 1 1 n , 5 n , 3 r , 2 r , 1 r , 4 1 p , 3 1 p , 2 1 p , 4 p 5 1 r , 4 1 r , 3 1 r , 1 1 r , 4 r . d e t c e n n o c t o n
4 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 pin description (continued) a1 ball pad indicator 13mm x 13mm cspbga package e6420 top view 13 mm x 13 mm cspbga g1 g2 g3 g5 g6 g7 g8 g9 g10 g11 g13 g14 e1 e2 e3 e5 d4 e4 f4 g4 h4 j4 k4 l4 m4 d5 d6 d7 d8 d9 d10 d11 d12 e12 f12 g12 h12 j12 k12 e6 e7 e8 e9 e10 e11 e13 e14 d1 d2 d3 d13 d14 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 b15 c15 d15 e15 f15 g15 h15 j15 k15 l15 m15 n15 p15 r15 b a c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 1011 1213 15 14 n1 n2 n3 n4 n5 n6 n7 n8 n9 n10 n11 n12 n13 n14 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 f1 f2 f3 f5 f6 f7 f8 f9 f10 f11 f13 f14 j1 j2 j3 j5 j6 j7 j8 j9 j10 j11 j13 j14 l1 l2 l3 l5 l6 l7 l8 l9 l10 l11 l12 m5 m6 m7 m8 m9 m10 m11 m12 l13 l14 m1 m2 m3 m13 m14 k1 k2 k3 k5 k6 k7 k8 k9 k10 k11 k13 k14 h1 h2 h3 h5 h6 h7 h8 h9 h10 h11 h13 h14 iout_ch1_0 iout_ch1_1 avcc vout_ch1_7 vout_ch1_10 vout_ch1_8 vout_ch1_9 vout_ch1_4 vout_ch1_5 vout_ch1_6 vout_ch1_1 vout_ch1_2 vout_ch1_3 iout_ch1_3 iout_ch1_4 vout_ch1_0 iout_ch2_3 iout_ch2_2 iout_ch1_2 vout_ch2_1 iout_ch2_4 vout_ch2_0 vout_ch2_4 vout_ch2_2 vout_ch2_3 vout_ch2_6 vout_ch2_5 vout_ch2_7 vout_ch2_9 avcc r_offset_c avdd agnd r_gain_f r_gain_c r_master r_offset_b dvdd dgnd vee r_gain_d r_gain_a r_offset_d r_offset_a vee r_gain_e r_gain_b avcc vout_ch2_8 iout_ch2_1 iout_ch2_0 vout_ch2_10 avdd dgnd vref avcc vout_ch0_8 vout_ch0_7 vout_ch0_5 vout_ch0_6 vout_ch0_3 vout_ch0_2 vout_ch0_4 vout_ch0_0 iout_ch0_4 vout_ch0_1 iout_ch3_2 iout_ch0_2 iout_ch0_3 vout_ch3_0 iout_ch3_4 iout_ch3_3 vout_ch3_3 vout_ch3_2 vout_ch3_1 vout_ch3_6 vout_ch3_5 vout_ch3_4 vout_ch3_9 vout_ch3_8 vout_ch3_7 vout_ch3_10 iout_ch3_0 iout_ch3_1 vout_ch0_9 iout_ch0_0 iout_ch0_1 vout_ch0_10 sdo test_mode dvdd agnd vee sdi scan_out reset* ck_out n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c update sgnd sgnd vee ce ck 1 144 142 139 136 134 131 128 125 122 119 116 113 111 109 8 76 11 10 9 14 13 12 17 16 15 20 19 18 23 21 22 26 24 25 28 27 29 31 30 32 104 102 103 101 99 100 97 96 98 94 93 95 90 91 92 87 88 89 84 85 86 81 82 83 78 79 80 3 2 141 138 135 132 129 127 124 121 118 115 112 110 108 5 4 143 140 137 133 130 126 123 120 117 114 107 105 106 34 33 35 42 45 48 51 54 58 61 65 68 71 76 77 36 38 40 43 46 49 52 55 57 60 63 66 69 74 75 37 39 41 44 47 50 53 56 59 62 64 67 70 72 73 top view note: balls populating the inner 9x9 grid are for improved thermal dissipation. this middle grid of balls should be connected to the vee plane or left floating. order e6420bbg if populated middle is desired.
5 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 pin description (continued) actual size a1 ball pad indicator 13mm x 13mm cspbga package g1 g8 e1 d8 e8 d1 c1 c8 b1 b8 a1 a8 b a c d e f g h j k l m n p r 1 8 10 n1 n8 p1 p8 r1 r8 f1 f8 j1 j8 l1 l8 m8 m1 k1 k8 h1 h8 vout_ch1_7 vout_ch1_4 vout_ch1_1 iout_ch1_3 iout_ch2_3 vout_ch2_1 vout_ch2_4 vout_ch2_6 vout_ch2_9 agnd dgnd vee dgnd agnd sgnd 1 128 8 11 14 17 20 23 26 28 31 3 127 5 126 34 54 36 55 37 g2 e2 d2 c2 b2 a2 2 n2 p2 r2 f2 j2 l2 m2 k2 h2 vout_ch1_8 vout_ch1_5 vout_ch1_2 iout_ch1_4 iout_ch2_2 iout_ch2_4 vout_ch2_2 vout_ch2_5 vout_ch2_8 144 7 10 13 16 19 21 24 27 30 2 4 33 38 39 d4 e4 f4 g4 h4 j4 k4 l4 m4 c4 b4 a4 4 n4 p4 r4 iout_ch1_1 avcc vout_ch2_10 iout_ch2_1 iout_ch1_0 139 138 140 42 43 44 g5 e5 d5 c5 b5 a5 5 n5 p5 r5 f5 j5 l5 m5 k5 h5 iout_ch2_0 r_master r_offset_d sdo reset* 136 135 137 45 46 47 g6 d6 e6 c6 b6 a6 6 n6 p6 r6 f6 j6 l6 m6 k6 h6 r_offset_c r_offset_b r_offset_a test_mode ck_out update 134 132 133 48 49 50 g7 d7 e7 c7 b7 a7 7 n7 p7 r7 f7 j7 l7 m7 k7 h7 avdd dvdd avdd dvdd sgnd 131 129 130 51 52 53 56 g9 d9 e9 c9 b9 a9 9 n9 p9 r9 f9 j9 l9 m9 k9 h9 r_gain_f vee r_gain_e vref vee vee n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c 125 124 123 58 57 59 g10 d10 e10 c10 b10 a10 n10 p10 r10 f10 j10 l10 m10 k10 h10 r_gain_c r_gain_d r_gain_b sdi ce 122 121 120 61 60 62 g11 d11 e11 c11 b11 a11 11 n11 p11 r11 f11 j11 l11 m11 k11 h11 iout_ch3_1 r_gain_a iout_ch3_0 iout_ch0_0 scan_out ck 119 118 117 65 63 64 d12 e12 f12 g12 h12 j12 k12 c12 b12 a12 12 n12 p12 r12 l12 m12 vout_ch3_10 avcc avcc vout_ch0_10 iout_ch0_1 116 115 114 68 66 67 g13 e13 d13 c13 b13 a13 13 n13 p13 r13 f13 j13 l13 m13 k13 h13 vout_ch0_7 vout_ch0_3 vout_ch0_0 iout_ch3_2 vout_ch3_0 vout_ch3_3 vout_ch3_6 vout_ch3_9 113 104 101 97 94 90 87 84 81 78 112 107 71 69 70 g14 e14 d14 c14 b14 a14 14 n14 p14 r14 f14 j14 l14 m14 k14 h14 vout_ch0_8 vout_ch0_5 vout_ch0_2 iout_ch0_4 iout_ch0_2 iout_ch3_4 vout_ch3_2 vout_ch3_5 vout_ch3_8 111 102 99 96 93 91 88 85 82 79 110 105 76 74 72 a15 b15 c15 d15 e15 f15 g15 h15 j15 k15 l15 m15 n15 p15 r15 15 vout_ch0_6 vout_ch0_4 vout_ch0_1 iout_ch0_3 iout_ch3_3 vout_ch3_1 vout_ch3_4 vout_ch3_7 vout_ch0_9 109 103 100 98 95 92 89 86 83 80 108 106 77 75 73 g3 e3 d3 c3 b3 a3 3 n3 p3 r3 f3 j3 l3 m3 k3 h3 vout_ch1_10 avcc vout_ch1_9 vout_ch1_6 vout_ch1_3 vout_ch1_0 iout_ch1_2 vout_ch2_0 vout_ch2_3 vout_ch2_7 142 6 9 12 15 18 22 25 29 32 141 143 35 40 41 bottom view note: balls populating the inner 9x9 grid are for improved thermal dissipation. this middle grid of balls should be connected to the vee plane or left floating. order e6420bbg if populated middle is desired.
6 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 circuit description grouping of dacs dacs are separated into 4 channels of 6 distinct functional groups. groups are defined by: type (voltage or current output) resolution (# of bits) output range output compliance. table 1 defines the dacs on a per channel basis: e t u b i r t t a p u o r g a p u o r g b p u o r g c p u o r g d p u o r g e p u o r g f f o # l a t o t p u o r g n i s c a d l e n n a h c r e p 5l e n n a h c r e p 2l e n n a h c r e p 2l e n n a h c r e p 2l e n n a h c r e p 2l e n n a h c r e p 3 e p y t vvvv i i n o i t u l o s e r ) s t i b f o # ( 3 13 13 13 13 16 : e g n a r t u p t u o ) 1 e t o n ( e g n a r c a d x a m e g n a r t e s f f o v 5 . 1 1 -v 5 . 2 o t v 5 . 3 v 5 . 1 1 -v 5 . 2 o t v 5 . 3 v 7 1 -v 5 . 2 o t v 5 . 3 v 5 . 1 1 -v 5 . 2 o t v 5 . 3 a m 6 . 3 b s l 8 2 1 ) 2 e t o n ( a m 6 . 3 0 t e s f f o t u p t u o e l b a t s u j d as e ys e ys e ys e yo no n e c n a i l p m o ca 0 0 1 a 0 0 1 a 0 0 1 a 0 0 1 v 2 . 2 d d v a o t 2 . 0 ) 3 e t o n ( v 2 . 2 d d v a o t 2 . 0 ) 3 e t o n ( table 1. dac grouping note 1: the max dac range is achieved through specific avcc, avee, and gain resistor settings. see the equations in the "dac voltage output overview", "dac current output overview", and specifications for details. note 2: 128 lsb is equivalent to 128 * lsb, where lsb = range / 2 13 . for max range case of 3.6 ma, this offset would thus be: 56.26 a of offset current at code 0. note 3: compliance specified in the table is at iout = 1.3ma. maximum compliance is lower at higher currents. please refer to specifications for compliance at other output currents. chip overview the edge6420 provides 64 output levels (44 voltage and 20 current). these outputs can easily be configured to generate the specific analog voltage and current requirements for 4 channels of ate pin electronics including: 3 level driver window comparator active load per pin pmu without requiring any scaling or shifting via external components. the edge6420 has the flexibility to be used in other configurations for other applications. programming of the chip is done using a 4 bit digital interface comprised of: serial data in clock update chip enable.
7 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 circuit description (continued) dac voltage output overview the output voltage of group a, b, c, and d dacs is governed by the following equation: equation 1. where: data corresponds to the base-10 value of the binary data loaded into the shift register shown in figure 2. k g[a:d] is a multiplying factor that is fixed, as follows: k ga = 4 k gb = 4 k gc = 8 k gd = 4 v ref = 2.5v offset the offset for each of the voltage dacs is governed by the following equation: equation 2. where: k offset = 2 v ref = 2.5v external resistors the recommended resistor values for the above equations are as follows: r_master = 100k ? (0.1% precision) r_gain_[a:d] = (0.4 to 1.15) * r_master r_offset_[a:d] = (0.0 to 1.2) * r_master minimum / maximum output voltages see table 2 for the minimum and maximum possible voltages of a voltage output. t able 2. minimum/maximum output voltages where: v offset[a:d] is defined in equation 2 and equation 3. the most negative voltage possible for the edge6420 is 3.5v when vee = 4.5v. resolution the resolution of the dacs in groups a, b, c, and d is: v range_[a:d] / 2 13 where v range_[a:d] is defined in equation 4. range the range of the dacs in groups a, b, c and d is: equation 4. v out_[a:d] = * k g[a:d] * v ref + v offset_[a:d] r_gain_[a:d] r_master * data 8192 v offset_[a:d] k offset r_offset_[a:d] r_master = * * 0.5 C v ref g n i t t e s c a d b s l . . . b s m v ] d : a [ _ t u o ) v ( h 0 0 0 0 v ] d : a [ _ t e s f f o h f f f 1 v ] d : a [ _ x a m v max_[a:d] = + v offset_[a:d] r_gain_[a:d] r_master k g[a:d] * v ref 8191 8192 * * = v range_[a:d] r_gain_[a:d] r_master 8191 8192 k g[a:d] v ref * * *
8 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 circuit description (continued) group a dacs there are five group a dacs/channel. group a dacs have a centralized offset, gain and range that is independent of any other group. group a dacs are characterized by 13 bit resolution and their typical outputs are governed by the following equation: where: note: v ref = 2.5v group b dacs there are two group b dacs/channel. group b dacs have a centralized offset, gain and range that is independent of any other group. group b dacs are characterized by 13 bit resolution and their typical outputs are governed by the following equation:. where: note: v ref = 2.5v group c dacs there are two group c dacs/channel. group c dacs have a centralized offset, gain and range that is independent of any other group'. group c dacs are characterized by 13 bit resolution and their typical outputs are governed by the following equation: where: note: v ref = 2.5v group d dacs there are two group d dacs/channel. group d dacs have a centralized offset, gain and range that is independent of any other group. group d dacs are characterized by 13 bit resolution and their typical outputs are governed by the following equation: where: note: v ref = 2.5v dac current output overview the output current of group e and f dacs is governed by the following equation: equation 5. where: data corresponds to the base-10 value of the binary data loaded into the shift resister in figure 2. k g[e:f] is a multiplying factor that is fixed, as follows: k ge = 80 k gf = 80 v ref = 2.5v max_count_e = 8192 max_count_f = 64 v out_a = = * 10 + v offset_a v offset_a r_gain_a r_master * data 8192 r_offset_a r_master 5 * .5 C v out_b = = * 10 + v offset_b v offset_b r_gain_b r_master * data 8192 r_offset_b r_master 5 * .5 C v out_c = = * 20 + v offset_c v offset_c r_gain_c r_master * data 8192 r_offset_c r_master 5 * .5 C v out_d = = * 10 + v offset_d v offset_d r_gain_d r_master * data 8192 r_offset_d r_master 5 * .5 C i out_[e:f] = + i offset_[e:f] k g[e:f] * i ref_[e:f] * data max_count_[e:f] i ref_[e:f] = v ref r_gain_[e:f]
9 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 circuit description (continued) offset the typical offset for each current dac is governed by the following equations: equation 6. i offset_f = 0 group e dacs there are 2 group e dacs/channel. group e dacs are characterized by: current outputs (current flows out of the chip) 13 bit resolution fixed offset ( 128 * lsb typical) adjustable full scale range (but < 3.6 ma). the output current equation for group e dacs is: where: 55 k ? r_gain_e 156 k ? note: v ref = 2.5v group f dacs there are 3 group f dacs/channel. group f dacs are characterized by: current outputs (current flows out of the chip) 6 bit resolution fixed offset (0 typical) adjustable full scale range (but < 3.6 ma). the output current equation for group f dacs is: where: 55 k ? r_gain_f 156 k ? note: v ref = 2.5v i out_e =C data * 8192 200 r_gain_e 3.125 r_gain_e i out_f = data * 64 200 r_gain_f i offset_e =C k ge * v ref * r_gain_e 128 max_count_e
10 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 circuit description (continued) s s e r d d al e n n a h cp u o r ge p y ts e s u l a c i p y t 0 1 2 3 4 0 0 0 0 0 a a a a a v v v v v s l e v e l r o t a r a p m o c & r e v i r d 5 6 0 0 b b v v s d l o h s e r h t r o t a r a p m o c u m p p 7 8 0 0 c c v v h s a l f , e g a t l o v e c r o f u m p p e g a t l o v r e p u s g n i m m a r g o r p 9 0 1 0 0 d d v v e g a t l o v g n i t a t u m m o c d a o l 1 1 2 1 0 0 e e i i k n i s d n a e c r u o s d a o l s t n e r r u c g n i m m a r g o r p 3 1 4 1 5 1 0 0 0 f f f i i i g n i l l a f / g n i s i r , s a i b p i h c t s u j d a e t a r w e l s 1 3 - 6 11 . 1 l e n n a h c r o f e v o b a s a t a m r o f e m a s 7 4 - 2 32 . 2 l e n n a h c r o f e v o b a s a t a m r o f e m a s 3 6 - 8 43 . 3 l e n n a h c r o f e v o b a s a t a m r o f e m a s 4 6a / nl l ai / vs c a d l l a r o f d a o l l e l l a r a p 5 5 2 - 5 6. ) y t i l i b a d a r g p u e r u t u f r o f d e v r e s e r ( d e s u t o n address map
11 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 circuit description (continued) figure 1. dac functionality block diagram d0:d12 (for parallel load) a0:a6 . . . . . . . . . dac 13 7 sdo ck_out dac output #1 dac output #0 24-bit shift register central dac latch (24 latches) reset reset load dq r decode and individual dac update programming logic update reset* ce ck sdi reset* this is a 13-bit latch for dac (note: there are some current output dacs that require only 6-bit latches) delay en r q l en r q l dac output #63 dac en r q l q63 q64 q0 q1 address decoder addr . . . . . . dac
12 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 circuit description (continued) programming sequence the dacs are programmed serially (see figures 1, 2a, 2b, and 3). on each rising edge of ck, sdi is loaded into a shift register. it requires 24 clocks to fully load the shift register (8 address bits + 16 data bits). for groups a, b, c, d, and e dacs: address and data are loaded lsb first, msb last. in a 24 clock sequence, a0, as shown in figure 2a, is loaded into the shift register on the first ck rising edge, and d15 is loaded last on the 24th rising ck edge. note that a 24th falling ck edge is required to transfer the data from the central dac latch to the selected dac latch (see figure 1). see detailed timing diagrams in the "ac characteristics" specifications section. for group f dacs: the loading sequence is the same as groups a-e, but group f uses only 6 bits, and these bits must be programmed as shown in figure 2b. 24 clock cycles are required for programming, with a0 loaded on the first rising ck edge, and d8 (as shown in figure 2b) loaded on the 24th rising ck edge. as is the case with other groups, a 24th falling edge of ck24 is required for proper programming of group f dacs. chip enable ce is a synchronous input which determines whether the central dac latch shown in figure 1 is loaded with data from the shift register. ce is also necessary to update a dac. if ce is high, rising edges of ck load data from the shift register to an internal latch. if ce is low, central dac latch updating is disabled. ce central and individual dac latch "load" status low central and individual dac latch loading is disabled high central and individual dac latches are loaded figure 2a. format of address and data in shift register for group a, b, c, d, and e dacs (13-bits) figure 2b. format of address and data in shift register for group f dacs (6-bits) figure 3. serial data programming sequence d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data a5 a4 a3 a2 a1 a0 address lsb bits reserved for future upgradability sdi a6 bits reserved for future upgradability lsb msb msb a7 d5 d8 d7 d6 d4 d3 d2 d1 d0 x x x x x x x a6 a5 a4 a3 a2 a1 a0 lsb bits reserved for future upgradability sdi a7 bits reserved for future upgradability "don't care" bits that must be included in programming sequence lsb msb msb data address a0 a1 a6 a7 d0 d1 d14 d15 lsb addr. msb addr. lsb data msb data sdi ck a1 ce update next set of data a0 ck1 update selected dac register sdo ck24 a0 a1 previous data corresponds to a0 loaded at ck1 t ck
13 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 circuit description (continued) digital outputs sdo is a cmos output, swinging rail to rail between dvdd and dgnd. chip reset and power up reset* for the edge6420 is active low. when the edge6420 first powers up, the latches will turn on to the same state as though reset* had been asserted. when reset* is brought low, the latches, and therefore the dac levels, will go to a known state that corresponds to a specific data code. see the "application information" section for an example of how this functionality works. the known states are: care should be taken to ensure reset* is invoked properly. it is critical to ensure that if a reset* is asserted after update has transitioned from a high to low state, that reset* stay low, at least 2 s. to understand this precaution, notice in figure 1 that update is delayed in order to enable individual dac latches. if reset* is not brought low for sufficient time, an individual dac update will occur. by simply forcing the reset* pulse low for a minimum of 2 s, when a ck frequency of 50 mhz or less is used, the 6420 will clear properly to the known states shown above. power supply sequence power supplies should be asserted in the following order: 1. vee 2. avdd 3. dvdd 4. avcc to avoid latchup and ensure a predictable power up, the above sequence should be followed. analog scan test feature voltage outputs each voltage output of the edge6420 has high impedance fet(s) connected from the outputs to a common analog scan line. the feature utilizes the normal address decoding, as shown on page 8, as well as a "high" level on the test_mode pin (see truth table below). to test an output, a dac should be loaded as shown by timing in figure 3. the clock should be stopped after the falling edge of ck24 after update is unasserted. at this point, the scan_out pin, which is an analog output, will reflect the voltage at the addressed dac's output pin. note that the scan output is switched off when the parallel load is selected (address 64). this prevents a parallel connection of all the dac outputs when the scan feature is used. figure 5. voltage output scan p u o r g) e d o c ( e t a t s * t e s e r ah 0 0 0 1 bh 0 0 0 1 ch 0 0 0 1 dh 0 0 0 1 eh 0 0 0 0 fh 0 0 0 1 e d o m _ t s e te t a t s n a c s 0f f o n a c s 1n o n a c s address decoder test_mode scan_out vout_ch0_1 vout_ch0_2 vout_ch0_3 note: when address 64 is invoked (parallel load), scan is disabled.
14 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 circuit description (continued) current outputs the test_mode and scan_out pins on the edge6420 are used in the same way as for voltage outputs. the scan circuits for current outputs are shown in figure 6. the voltage measured at the scan_out pin, using the configuration in figure 6, for group e and f current outputs are as follows: v scan_out_e = (r sense_e + r pad ) * i out_e where: r sense_e = 400 ? 30% r pad = 30 ? 30% and v scan_out_f = (r sense_f + r pad ) * i out_f where: r sense_f = 400 ? 30% r pad = 30 ? 30% the typical "on" resistance of the fet switch is 100 k ? , but can vary from 60 k ? to 180 k ? as a function of process and output voltage. notes when using scan feature with multiple chips when multiple 6420s are used on a board, and it is desired to gang the scan_out pins of these 6420s, or gang the test_mode inputs to one point, it is required for proper functioning that the following rules be followed: 1) if test_mode inputs are ganged together, scan_out cannot be ganged, or invalid results will be observed at the scan_out pin. hence, each scan_out pin on a 6420 will have to be measured separately. 2) if scan_out is ganged, test_mode pins cannot be ganged together. figure 6. current output scan circuits address decoder + iout_ch0_0 test_mode scan_out idac + iout_ch0_1 idac + iout_ch0_2 idac connect to virtual ground connect to virtual ground note: when address 64 is invoked (parallel load), scan is disabled. connect to virtual ground r sense r sense r pad r pad r pad r sense
15 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 application information one application for the edge6420 is to provide necessary dc voltages and currents for 4 channels of pin electronics (driver, receiver, load) and per pin measurement units. for example, using the: edge720 load / driver / comparator edge4707 ppmu with the following specifications: edge720 1.5 < driver output high < +7.5v 1.5 < driver output low < +7.5v 1.5 < comparator threshold high < +7.5v 1.5 < comparator threshold low < +7.5v 1.5 < commutating voltage < 7.5v 0 < load source current < 24 ma 0 < load sink current < 24 ma edge 4707 ppmu 2.8 < ppmu (mi) compare high voltage < +2.8v 2.8 < ppmu (mi) compare low voltage < +2.8v 3.0 < ppmu (fv) < +14.0v other 0 < flash programming voltage (vhh) < +14v table 8 demonstrates edge6420 settings that can be used to fulfill the above requirements. power supplies (for this application): 15.25 avcc 15.75v 4.75v vee 4.25v 4.6v avdd 5.25v 4.85 dvdd 5.15v agnd = 0, sgnd = 0 table 8. application chart ?possible chip specification l e n n a h c 0 s s e r d d a p u o r ge p y ts t i b #n o i t u l o s e rt e s f f o g n i t l u s e r e g n a r t u p t u o e c n a i l p m o c t e s e r n o r e w o p ) e d o c c a d ( d e t s e g g u s n o i t a c i l p p a 0 1 2 3 4 av 3 1v m 0 1 . 1v 5 . 1 v 5 . 7 + / 5 . 1 a 0 0 1 ) v 3 ( h 0 0 0 1 h i v l i v h o v l o v 1 m o c v 5 6 bv 3 1v m 4 8 6 . 0v 8 . 2 v 8 . 2 / 8 . 2 a 0 0 1 ) v 0 ( h 0 0 0 1 h c u m p p l c u m p p 7 8 cv 3 1v m 7 0 . 2v 0 . 3 v 0 . 4 1 + / 0 . 3 a 0 0 1 ) v 6 ( h 0 0 0 1 v f u m p p h h v 9 0 1 dv 3 1v m 0 1 . 1v 5 . 1 v 5 . 7 + / 5 . 1 a 0 0 1 ) v 3 ( h 0 0 0 1n i _ m c v 1 1 2 1 ei 3 1a n 9 5 1a / na m 3 . 1 o t 0 v 4 . 2 / 2 . ) 1 e t o n ( ) a m 0 ( h 0 0 0 0 n i _ c s i n i _ k s i 3 1 4 1 5 1 fi6 a 9 3a / na m 5 . 2 o t 0v 1 . 2 / 2 . ) 1 e t o n ( ) a m 0 . 1 ( h 0 0 0 1 j d a r j d a f s a i b i 1 3 6 1 . 1 l e n n a h c r o f e v o b a s a e m a s 7 4 2 3 . 2 l e n n a h c r o f e v o b a s a e m a s 3 6 8 4 . 3 l e n n a h c r o f e v o b a s a e m a s note 1: max compliance depends on maximum current required. see specifications for limits.
16 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 application information (continued) figure 7. required external resistors and components vout_ch0_0 vout_ch0_1 vout_ch0_2 iout_ch0_1 iout_ch0_4 vout_ch0_8 vout_ch0_9 vout_ch0_10 dac voltage outputs vref dvdd dgnd agnd vee edge6420 avcc avdd +15.5v sgnd 0v +5v 5v 0v 0v +5v 2.5v agnd . . . . . . dac current outputs . . . . . . loading requirement: 10 nf to 100 nf loading requirement: 1 nf (see below) loading requirement: 1 nf (see below) loading requirement: 10 nf to 100 nf note: all unused voltage outputs must have an external capacitor attached (between 10 nf and 100 nf). i ref r_master r_gain_a i ref r_offset_a i ref r_gain_b i ref r_offset_b i ref r_gain_c i ref r_offset_c i ref r_gain_d i ref r_offset_d i ref i ref_e i ref_f r_gain_e r_gain_f for group a dacs gain and offset control for group b dacs gain and offset control for group c dacs gain and offset control for group d dacs gain and offset control agnd the selection of r_master establishes i ref + loading requirements voltage outputs all voltage outputs (denoted vout_ch[0:3]_[0:10]) require a load capacitance between 10 nf and 100 nf for stability. current outputs all current outputs require capacitive loading; the amount of loading needed to ensure stability is dependent on the impedance that the current outputs of the 6420 drive. for impedances of 1.3 k ? to 1.6 k ? , such as what is seen at the e720 current inputs (isk, isrc, ibias, radj, and fadj), it is recommended that 1 nf be used. caution on exceeding compliance limits on current output dacs current output dacs (i.e., group e and f dacs) can exhibit a lock-up condition in situations when the actual voltage seen at the outputs of these dacs exceeds the compliance limits in the specification. care should be taken in the design of circuits being driven by group e and f outputs to ensure compliance limits stated in the specifications are not exceeded.
17 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 care should be taken to ensure that devices being driven by group e and f dacs are designed to be within the compliance specification. figure 8. compliance of current output dacs (groups e and f) caution regarding power dissipation of the 6420 during parallel load: the voltage dac output amplifiers, for a fast process, can: source up to 10 ma (8 ma @ tj = 100 ? c) sink up to 4.5 ma (3.5 ma @ tj = 100 ? c) caution must be taken during a parallel load, particularly when the voltage dacs are loaded with a large filtering capacitor (10 to 100 nf). in this scenario, a large voltage change can induce a large current peak. for example, the currents calculated below can be induced in the vcc/ vee supplies: source case: 44 dacs * 10 ma / dac + 40 ma = 480 ma (or 400 ma @ tj = 100 ? c) in the vcc supply sink case: 44 dacs * 4.5 ma / dac + 120 ma = 320 ma (or 280 ma @ tj = 100 ? c) in the vee supply therefore, the user must take care of extra power dissipation due to these currents peaks , and should avoid large voltage changes during a parallel load. temperature coefficient effect on dacs there is a gain and offset temperature coefficient that should be taken into account in the system design that will affect calibration and performance. the equation for voltage drift on output dacs is as follows: ? v out_a,b,c,d = ? t * tc offset_a,b,c,d + code * lsb * tc gain_a,b,c,d (%/ ? c) current outputs drift follow the following equation: ? i out_e,f = ? t * tc offset_e,f + code * lsb * tc gain_e,f (%/ ? c) average values for tc offset and tc gain can be found in the specifications. compliance of current output dacs (groups e, f) the compliance of the current output dacs (groups e and f) is governed by the following two equations: i out < 2.5 ma: v compliance = ( 250 ? * i out ) + avdd 1.875v i out 2.5 ma: v compliance = ( 600 ? * i out ) + avdd 1v see figure 8 for a graphical depiction. note: i out is current sourced from output of dac. application information (continued) a ? c v ? c 1 ma 2 ma 3 ma i out avdd avdd C 1 avdd C 2 avdd C 3 v compliance (1.3 ma, avdd C 2.2v) (2.5 ma, avdd C 2.5v) (3.6 ma, avdd C 3.2v) compliance exceeded
18 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 package information (continued) 151413121110987654321 a b c d e f g h j k l m n p r d d2 e (e1) (d1) e2 ? ? 0.10 detail b detail a 4 nx 0.15 m c a m b m b 0.075 m c f e f seating plane 5 6 // bbb c aaa c // ccc c a2 a1 a c ? top view bottom view side view detail b detail a edge6420bbg package s e c n e r e f e r l a n o i s n e m i d f e rn i mm o nx a m a6 9 . 06 0 . 16 1 . 1 1 a1 2 . 06 2 . 01 3 . 0 2 a0 5 . 05 5 . 00 6 . 0 1 dc s b 0 2 . 1 1 2 d0 9 . 2 10 0 . 3 10 1 . 3 1 e0 9 . 2 10 0 . 3 10 1 . 3 1 1 ec s b 0 2 . 1 1 2 e0 9 . 2 10 0 . 3 10 1 . 3 1 b0 4 . 05 4 . 05 5 . 0 c5 2 . 0 a a a2 1 . 0 b b b0 2 . 0 c c c0 2 . 0 e8 . 0 f0 8 . 00 9 . 00 0 . 1 m5 1 n5 2 2 notes: 1. all dimensions are in millimeters. 2. e represents the basic solder ball grid pitch. 3. m represents the basic solder ball matrix size, and symbol n is the number of balls after depopulating. 4. b is measurable at the maximum solder ball dimaeter after reflow parallel to primary datum c . 5. dimension aaa is measured parallel to primary datum c . 6. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 7. package surface shall be matte finish charmilles 24 to 27. 8. package centering to substrate shall be 0.0780 mm maximum for both x and y directions respectively. 9. package warp shall be 0.050 mm maximum. 10. substrate material base is bt resin. 11. the overall package thickness a already considers collapse balls. 12. dimensioning and tolerancing per asme y14.5m 1994. note: the inner 9x9 balls are for improved thermal dissipation. they will be at the vee potential, so board layout should ensure that these inner balls are connected to the vee plane.
19 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 recommended operating conditions r e t e m a r a pl o b m y sn i mp y tx a ms t i n u y l p p u s r e w o p g o l a n a e v i t i s o pc c v a5 2 . 5 1 +5 . 5 1 +5 7 . 5 1 +v 2 y l p p u s r e w o p g o l a n a e v i t i s o pd d v a6 . 4 +5 +5 2 . 5 +v y l p p u s r e w o p e v i t a g e ne e v 5 2 . 5 5 3 . 4v ) 2 e t o n ( e g a t l o v e c n e r e f e rf e r v0 0 5 . 2v ) 1 e t o n ( d n u o r g y l p p u sd n g s5 2 . 05 2 . +v 1 y l p p u s g o l a n a l a t o tc c v a e e v5 . 0 23 2 +v y l p p u s r e w o p l a t i g i dd n g d d d v d0 0 . 30 . 50 5 . 5v ) 1 e t o n ( d n u o r g l a t i g i dd n g d5 2 . 05 2 . +v ) g b b 0 2 4 6 ( e g a k c a p f o e c n a t s i s e r l a m r e h t ) e g a k c a p f o r e t n e c - p o t t a d e r u s a e m ( c j 3 ? w / c ) e g a k c a p f o p o t t a ( e r u t a r e p m e t e s a ct e s a c 0 40 8 c ? all power supply voltages are referred to agnd, the reference signal ground, unless othewise specified. note 1: not production tested. note 2: user should use a precision supply for vref setting because the offset and gain of all dacs will change proportionately to a deviation from vref = 2.500v. see equations 1 and 5 to determine the extent of offset and gain change to deviations in vref.
20 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 absolute maximum ratings all power supply voltages are referred to agnd, the reference signal ground, unless othewise specified. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. exposure to absolute maximum conditions for extended periods may affect device reliability. note 1: exceeding this limit may result in a monostable output state at maximum current. note 2: full scale step definition: 11.5v step for group a, b, d dacs, 20v step for group c, 3.6 ma steps for groups e and f. r e t e m a r a pl o b m y sn i mx a ms t i n u y l p p u s g o l a n a e v i t i s o p 2 y l p p u s g o l a n a e v i t i s o p y l p p u s g o l a n a e v i t a g e n c c v a d d v a e e v . 5 3 5 3 . 5 . 5 0 2 + 5 . 5 + 5 3 . + v v v y l p p u s r e w o p l a t i g i dd n g d d d v d5 3 . 5 . 5 +v y l p p u s r e w o p l a t o tc c v a e e v c c v a d d v a d n g d d n g s 5 3 . 5 . 5 5 3 . 5 3 . 5 2 + 0 2 + 5 3 . + 5 3 . + v v v v s e g a t l o v t u p n i l a t i g i d , * t e s e r , e t a d p u , k c , e c e d o m _ t s e t , i d s 5 3 . d n g d5 3 . + d d v dv s e g a t l o v t u p n i g o l a n av f e r v , r e t s a m , v ] d : a [ _ t e s f f o ,v ] f : e [ _ n i a g v ] d : a [ _ n i a g 5 3 . d n g a 5 3 . e e v a 5 3 . + d d v a 5 3 . + d n g a v v s t n e r r u c t u p n i g o l a n a i ] f : e [ _ n i a g i r e t s a m 1 1 1 + 1 + a m a m s e g a t l o v t u p t u o g o l a n a d , c , b , a s p u o r g f , e s p u o r g ] d : a [ _ t u o v ] f : e [ _ t u o v 5 3 . e e v a 5 3 . d n g a 5 3 . + c c v a 5 3 . + d d v a v v s t n e r r u c t u p t u o g o l a n a t n e r r u c c d s u o u n i t n o c d , c , b , a s p u o r g] d : a [ _ t u o i0 0 3 0 0 3 +a ) 1 e t o n ( ) f , e s p u o r g ( e c n a i l p m o c e g a t l o v t u p t u o 3 . 3v e v i s s e c c u s n e e w t e b d e r i u q e r e m i t m u m i n i m s c a d 4 6 l l a f o s d a o l l e l l a r a p c @ d a o l ) 2 e t o n ( s p e t s e l a c s l l u f , f n 0 0 1 = n i m t2 s m e r u t a r e p m e t e g a r o t s e r u t a r e p m e t n o i t c n u j e r u t a r e p m e t g n i r e d l o s ) n i p e h t m o r f " 5 2 . , s d n o c e s 5 ( s t j t l o s t 5 60 5 1 + 5 2 1 + 0 6 2 + c ? c ? c ?
21 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 dc characteristics r e t e m a r a pl o b m y sn i mp y tx a ms t i n u , e t a d p u , k c , e c , i d s ( s t u p n i l a t i g i d ) e d o m _ t s e t , * t e s e r e g a t l o v w o l t u p n i e g a t l o v h g i h t u p n i t n e r r u c t u p n i l i v h i v h i i , l i i 4 . 2 1 8 . 1 v v a ) t u o _ k c , 0 d s ( s t u p t u o l a t i g i d i @ e g a t l o v w o l t u p t u o l o a m 6 . 1 = i @ e g a t l o v h g i h t u p t u o h o a m 4 . 0 = l o v h o v4 . 2 4 . d d v d v v s t u p t u o c a d ) s t u p t u o e g a t l o v ( d , b , a s p u o r g n o i t u l o s e r 3 1s t i b e g n a r e g a t l o v t u p t u o x a m 4 . = r e t s a m _ r / n i a g _ r @ 1 = r e t s a m _ r / n i a g _ r @ 5 1 . 1 = r e t s a m _ r / n i a g _ r @ e g n a r _ t u o v 8 . 9 4 0 1 5 . 1 1 2 . 0 1 v v v ) h 0 0 0 0 = a t a d ( e g n a r t e s f f o t u p t u o 0 . 0 = r e t s a m _ r / t e s f f o _ r @ 5 . 0 = r e t s a m _ r / t e s f f o _ r @ 0 . 1 = r e t s a m _ r / t e s f f o _ r @ 2 . 1 = r e t s a m _ r / t e s f f o _ r @ v t e s f f o 0 6 . 2 5 . 2 0 5 . 2 5 . 3 5 3 . 2 v v v v e c n a i l p m o c t n e r r u c t u p t u o 0 0 1 0 0 1 +a s t u p t u o e g a t l o v f o m o o r d a e h ) 1 e t o n ( ) t i m i l e c n a i l p m o c t n e r r u c g n i n i a t n i a m e l i h w ( c c v o t ) x a m ( t u o v e e v o t ) n i m ( t u o v ) x a m ( t u o v c c v a e e v ) n i m ( t u o v 5 2 . 1 0 0 . 1 v v t n i o p 9 h t i w r o r r e y t i r a e n i l l a r g e t n i ) 2 e t o n ( n o i t a r b i l a c 5 . 2 5 . 2b s l t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i ) 4 e t o n ( n o i t a r b i l a c 5 1 5 1b s l r o r r e y t i r a e n i l l a i t n e r e f f i d 1 1b s l ) 6 , 3 s e t o n ( o c p m e t n i a gc t d , b , a _ n i a g 5 8 2 0 0 . c ? / % ) 6 , 3 s e t o n ( o c p m e t t e s f f o 0 . 0 = r e t s a m _ r / t e s f f o _ r @ 5 . 0 = r e t s a m _ r / t e s f f o _ r @ 0 . 1 = r e t s a m _ r / t e s f f o _ r @ 2 . 1 = r e t s a m _ r / t e s f f o _ r @ c t d , b , a _ t e s f f o 8 8 2 0 1 1 5 4 1 + 1 3 2 + c ? / v c ? / v c ? / v c ? / v
22 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 dc characteristics (continued) r e t e m a r a pl o b m y sn i mp y tx a ms t i n u ) s t u p t u o e g a t l o v ( c p u o r g n o i t u l o s e r 3 1s t i b e g n a r e g a t l o v t u p t u o x a m ) h f f f i = a t a d ( 4 . = r e t s a m _ r / n i a g _ r @ 6 . = r e t s a m _ r / n i a g _ r @ 5 8 . = r e t s a m _ r / n i a g _ r @ e g n a r _ t u o v 5 7 . 6 1 8 2 1 7 12 2 . 7 1 v v v e g n a r t e s f f o t u p t u o ) h 0 0 0 0 = a t a d ( @ 0 . 0 = r e t s a m _ r / t e s f f o _ r @ 5 . 0 = r e t s a m _ r / t e s f f o _ r @ 1 . 1 = r e t s a m _ r / t e s f f o _ r @ 2 . 1 = r e t s a m _ r / t e s f f o _ r v t e s f f o 0 1 . 3 5 . 2 0 0 . 3 5 . 3 9 . 2 v v v v e c n a i l p m o c t n e r r u c t u p t u o0 0 1 0 0 1 +a c p u o r g s t u p t u o e g a t l o v f o m o o r d a e h ) t i m i l e c n a i l p m o c t n e r r u c g n i n i a t n i a m e l i h w ( ) 1 e t o n ( c c v o t ) x a m ( t u o v e e v o t ) n i m ( t u o v ) x a m ( t u o v c c v a e e v ) n i m ( t u o v 5 2 . 1 0 0 . 1 v v t n i o p 9 h t i w r o r r e y t i r a e n i l l a r g e t n i ) 2 e t o n ( n o i t a r b i l a c 3 3b s l t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i ) 4 e t o n ( n o i t a r b i l a c 0 2 0 2b s l r o r r e y t i r a e n i l l a i t n e r e f f i d1 1b s l ) 6 , 3 s e t o n ( o c p m e t n i a gc t c _ n i a g 2 1 0 0 . c ? / % ) 6 , 3 s e t o n ( o c p m e t t e s f f o @ 0 . 0 = r e t s a m _ r / t e s f f o _ r @ 5 . 0 = r e t s a m _ r / t e s f f o _ r @ 1 . 1 = r e t s a m _ r / t e s f f o _ r @ 2 . 1 = r e t s a m _ r / t e s f f o _ r c t c _ t e s f f o 0 5 2 7 7 0 4 2 + 6 6 1 + c ? / v c ? / v c ? / v c ? / v
23 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 dc characteristics (continued) r e t e m a r a pl o b m y sn i mp y tx a ms t i n u ) s t u p t u o t n e r r u c ( e p u o r g n o i t u l o s e r 3 1s t i b e g n a r t n e r r u c t u p t u o x a m k 5 5 = e _ n i a g _ r @ ? k 5 . 2 6 = e _ n i a g _ r @ ? k 6 5 1 = e _ n i a g _ r @ ? t u o i 9 0 . 3 6 . 3 2 . 3 8 2 . 1 5 3 . 3 a m a m a m ) 6 , 1 s e t o n ( e c n a i l p m o c e g a t l o v t u p t u o a m 3 . 1 @ a m 5 . 2 @ a m 2 . 3 @ a m 6 . 3 @ 0 2 . 0 0 2 . 0 0 2 . 0 0 2 . 0 0 2 . 2 d d v a 0 5 . 2 d d v a 2 9 . 2 d d v a 0 2 . 3 d d v a v v v v t n i o p 9 h t i w r o r r e y t i r a e n i l l a r g e t n i ) 2 e t o n ( n o i t a r b i l a c 2 2b s l t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i ) 4 e t o n ( n o i t a r b i l a c 5 1 5 1b s l r o r r e y t i r a e n i l l a i t n e r e f f i d1 1b s l t e s f f o t n e r r u c ) b s l * 8 2 1 ( 0 2 b s l * 8 2 1) b s l * 8 2 1 ( 0 2 + a ) 6 , 3 s e t o n ( o c p m e t n i a gc t e _ n i a g 1 2 0 0 . c ? / % ) 6 , 3 s e t o n ( o c p m e t t e s f f oc t e _ t e s f f o 0 0 1 c ? / a n ) s t u p t u o t n e r r u c ( f p u o r g n o i t u l o s e r 6s t i b e g n a r t n e r r u c t u p t u o x a m k 5 5 = f _ n i a g _ r @ ? k 5 . 2 6 = f _ n i a g _ r @ ? k 6 5 1 = f _ n i a g _ r @ ? t u o i 9 0 . 3 4 5 . 3 5 1 . 3 6 2 . 1 5 3 . 3 a m a m a m ) 6 , 1 s e t o n ( e c n a i l p m o c e g a t l o v t u p t u o a m 3 . 1 @ a m 5 . 2 @ a m 5 1 . 3 @ a m 6 . 3 @ 0 2 . 0 0 2 . 0 0 2 . 0 0 2 . 0 0 2 . 2 d d v a 0 5 . 2 d d v a 9 8 . 2 d d v a 0 2 . 3 d d v a v v v v h t i w r o r r e y t i r a e n i l l a r g e t n i ) 5 e t o n ( n o i t a r b i l a c t n i o p 2 5 2 . 0 5 2 . 0b s l r o r r e y t i r a e n i l l a i t n e r e f f i d1 1b s l t e s f f o t n e r r u c0 2 00 2a ) 6 , 3 s e t o n ( o c p m e t n i a gc t f _ n i a g 7 5 0 0 . c ? / % ) 6 , 3 s e t o n ( o c p m e t t e s f f oc t f _ t e s f f o 3 2 c ? / a n
24 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 note 1: not production tested. guaranteed by bench characterization. note 2: the 9 calibration points recommended are: data values of 0000h, 03ffh, 07ffh, 0bffh, offfh, 13ffh, 17ffh, 1bffh, 1fffh. note 3: assuming r_master = 100 k ? , stable vref, nominal external resistor values, and stable supply voltage values. note 4: calibration points are: data values of 0000h and 1fffh. note 5: calibration points are: data values of ooooh and oo3fh. note 6: see applications information for further information. dc characteristics (continued) all specifications are guaranteed over recommended operating conditions unless otherwise noted. dc test conditions (unless otherwise specified): vref = 2.50v. power supplies r e t e m a r a pl o b m y sn i mp y tx a ms t i n u n o i t p m u s n o c y l p p u s r e w o p ) 6 e t o n ( 1 y l p p u s g o l a n a e v i t i s o p ) 6 e t o n ( 2 y l p p u s g o l a n a e v i t i s o p ) 6 e t o n ( y l p p u s l a t i g i d ) 6 e t o n ( 1 y l p p u s r e w o p e v i t a g e n y l p p u s e c n e r e f e r c c i d d a i d d d i e e i f e r i 8 1 1 5 . 0 2 0 6 2 3 7 2 . 0 5 . 1 4 2 3 1 0 1 4 . 1 a m a m a m a m a m ) 1 e t o n ( o i t a r n o i t c e j e r y l p p u s r e w o p z h m 5 z h m 1 z h k 0 0 1 r r s p 5 6 5 4 0 5 b d b d b d ) 1 e t o n ( y t i v i t i s n e s c d y l p p u s r e w o p ? / t u o v ? d d v a 0 4b d
25 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 ac characteristics r e t e m a r a pl o b m y sn i mp y tx a ms t i n u s t u p n i l a t i g i d ) 1 e t o n ( s e m i t p u t e s k c g n i s i r o t i d s 4 2 k c g n i s i r o t ) e g d e g n i s i r ( e c 4 2 k c g n i s i r o t ) e g d e g n i s i r ( e t a d p u ) 3 , 2 s e t o n ( t i d s _ u s t e c _ u s t t d p u _ u s 0 1 0 1 5t f o % 0 7 k c s n s n s n ) 1 e t o n ( s e m i t d l o h k c g n i s i r o t i d s 4 2 k c g n i s i r o t ) e g d e g n i l l a f ( e c 4 2 k c g n i s i r o t ) e g d e g n i l l a f ( e t a d p u ) 3 , 2 s e t o n ( t i d s _ d l h t e c _ d l h t t d p u _ d l h 0 1 0 1 5t f o % 0 7 k c s n s n s n k c ) 5 , 1 s e t o n ( v 0 3 . v 3 . 3 = d d v d t a x a m f ) 5 e t o n ( e l c y c y t u d % 0 5 o t 0 3 e l c y c y t u d % 0 7 f x a m 3 3 0 2 z h m z h m ) 5 , 4 s e t o n ( 0 5 . v 0 . 5 = d d v d t a x a m f e l c y c y t u d % 0 5 o t 0 3 e l c y c y t u d % 0 7 f x a m 5 5 5 3 z h m z h m ) 1 e t o n ( e l c y c y t u dw p k c 0 30 50 7% h t d i w e s l u p t e s e rw p t e s e r 2s ) 1 e t o n ( e m i t g n i l t t e s e g a t l o v t u p t u o k c m o r f ( ) e t a d p u o t g n i d n o p s e r r o c ) r s f % 5 2 0 . 0 o t ( v 0 1 , p e t s e l a c s l l u f d , b , a s p u o r g r o f f n 0 1 : d a o l f n 0 0 1 : d a o l s t 0 3 0 5 2 0 7 0 0 7 s s ) r s f % 5 2 0 . 0 o t ( v 7 1 , p e t s e l a c s l l u f c p u o r g r o f f n 0 1 : d a o l f n 0 0 1 : d a o l 0 5 0 1 4 . 0 0 5 1 1 s s m e m i t g n i l t t e s t n e r r u c t u p t u o ) % 5 2 0 . o t ( e p u o r g f n 1 : d a o l f n 0 1 : d a o l 3 5 0 3 2 0 0 1 0 0 5 s s ) % 8 . o t ( f p u o r g f n 1 : d a o l f n 0 1 : d a o l 4 . 4 9 2 0 1 0 5 s s figure 8. shift register loading timing diagram figure 9. central and individual dac updating test conditions (unless otherwise specified): "recommended operating conditions". note 1: not production tested. guaranteed by design and characterization. note 2: the max spec of 70% of t ck is not production tested. note 3: ck24 refers to 24th rising clock edge, which corresponds to a full shift register. note that a falling ck24 edge is also required for proper operation of circuit. note 4: the 6420 is production tested at 55 mhz only, with 50% duty cycle. note 5: duty cycle % shown refers to high duration of clock in a period. sdi ck ck1 ck24 valid data a0 valid data d15 t su_sdi t su_sdi t hld_sdi t hld_sdi ce ck update ck24 ck1 t hld_ce t su_ce t ck t hld_update t su_update note: a 24th falling ck edge is required for dac updating!
26 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 ordering information contact information semtech corporation high-performance division 10021 willow creek rd., san diego, ca 92131 phone: (858)695-1808 fax (858)695-2633 r e b m u n l e d o me g a k c a p g b b 0 2 4 6 ea g b m m 3 1 x m m 3 1 , l l a b 5 2 2 m v e 0 2 4 6d r a o b n o i t a u l a v e 0 2 4 6 e g d e
27 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 revision history current revision: april 29, 2002 previous revision: september 25, 2001 # e g a pe m a n n o i t c e sn o i s i v e r s u o i v e r p n o i s i v e r t n e r r u c l l al l ay r a n i m i l e r p . " y r a n i m i l e r p " e v o m e r . " l a n i f " w o n t e e h s a t a d 1n o i t p i r c s e d. e c a f r e t n i l a i r e s t i b 1 a g n i s u d e m m a r g o r p e r a s c a d e h t . e c a f r e t n i l a i r e s a g n i s u d e m m a r g o r p e r a s c a d e h t 5 , 4 , 3s n o i t p i r c s e d n i p : d d a s r e b m u n l l a b ) t c e n n o c o n ( c / n 0 1p a m s s e r d d ad b te g a t l o v g n i t a t u m m o c d a o l 7 1n o i t a m o r f n i e g a k c a p : e v o m e r e g a k c a p g b a 0 2 4 6 e g d e 1 2s c i t s i r e t c a r a h c c dd , b , a s p u o r g n o i t a r b i l a c t n i o p 9 h t i w r o r r e y t i r a e n i l l a r g e t n i 2 : x a m n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 5 1 : x a m r o r r e y t i r a e n i l l a i t n e r e f f i d 1 < : x a m d , b , a s p u o r g n o i t a r b i l a c t n i o p 9 h t i w r o r r e y t i r a e n i l l a r g e t n i 5 . 2 : x a m , 5 . 2 : n i m n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 5 1 : x a m , 5 1 : n i m r o r r e y t i r a e n i l l a i t n e r e f f i d 1 : x a m , 1 : n i m 2 2s c i t s i r e t c a r a h c c dc p u o r g n o i t a r b i l a c t n i o p 9 h t i w r o r r e y t i r a e n i l l a r g e t n i 3 : x a m n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 0 2 : x a m r o r r e y t i r a e n i l l a i t n e r e f f i d 1 < : x a m d , b , a s p u o r g n o i t a r b i l a c t n i o p 9 h t i w r o r r e y t i r a e n i l l a r g e t n i 3 : x a m , 3 : n i m n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 0 2 : x a m , 0 2 : n i m r o r r e y t i r a e n i l l a i t n e r e f f i d 1 : x a m , 1 : n i m 3 2s c i t s i r e t c a r a h c c de p u o r g n o i t a r b i l a c t n i o p 9 h t i w r o r r e y t i r a e n i l l a r g e t n i 2 : x a m n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 5 1 : x a m r o r r e y t i r a e n i l l a i t n e r e f f i d 1 < : x a m e s p u o r g n o i t a r b i l a c t n i o p 9 h t i w r o r r e y t i r a e n i l l a r g e t n i 2 : x a m , 2 : n i m n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 5 1 : x a m , 5 1 : n i m r o r r e y t i r a e n i l l a i t n e r e f f i d 1 : x a m , 1 : n i m 4 2s c i t s i r e t c a r a h c c d f p u o r g n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 5 2 . 0 : x a m r o r r e y t i r a e n i l l a i t n e r e f f i d 1 < : x a m f p u o r g n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 5 2 . 0 : x a m , 5 2 . 0 : n i m r o r r e y t i r a e n i l l a i t n e r e f f i d 1 : x a m , 1 : n i m 4 2s e i l p p u s r e w o py l p p u s r e w o p e v i t a g e n : e v o m n m u l o c n i m o t x a m m o r f 8 1 1 5 2s c i t s i r e t c a r a h c c a c p u o r g r o f v 7 1 , p e t s e l a c s l l u f 0 1 4 : p y t , f n 0 0 1 : d a o l c p u o r g r o f v 7 1 , p e t s e l a c s l l u f 0 1 4 . 0 : p y t , f n 0 0 1 : d a o l 6 2n o i t a m r o f n i g n i r e d r o : e v o m e r g b a 0 2 4 6 e
28 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 revision history current revision: september 25, 2001 previous revision: august 3, 2001 # e g a pe m a n n o i t c e sn o i s i v e r s u o i v e r pn o i s i v e r t n e r r u c 6 1 n o i t a c i l p p a n o i t a m r o f n i 0 2 4 6 e h t f o n o i t a p i s s i d r e w o p g n i d r a g e r n o i t u a c d a o l l e l l a r a p g n i r u d n o i t c e s e r i t n e d r o w e r 9 1 d e d n e m m o c e r s n o i t i d n o c g n i t a r e p o 1 y l p p u s r e w o p e v i t a g e n ) 3 , 1 s e t o n ( 2 d n u o r g g o l a n a : e t e l e d s c e p s l l a m o r f ) d n g a o t d e r r e f e r ( y l p p u s r e w o p e v i t a g e n ) 1 e t o n ( d n u o r g y l p p u s : e t e l e d d n u o r g g o l a n a 2 e t o n w e n s e m o c e b 4 e t o n , 3 , 2 e t o n e t e l e d : s e t o n : d d a s e t o n f o g n i n n i g e b t a " . . . s e g a t l o v y l p p u s r e w o p l l a " 0 2s g n i t a r x a m b a 2 y l p p u s g o l a n a e v i t i s o p d d v d : m y s , y l p p u s r e w o p l a t i g i d y l p p u s r e w o p l a t o t d n g a d n g s , e n g a d n g d 5 3 . : n i m d n g d d d v d : m y s , y l p p u s r e w o p l a t i g i d y l p p u s r e w o p l a t o t d n g s , d n g d : e t e l e d s c e p s d n g a e e v d n a d n g a d d v a : d d a s e t o n f o g n i n n i g e b t a " . . . s e g a t l o v y l p p u s r e w o p l l a " 1 2s c i t s i r e t c a r a h c c d e g n a r e g a t l o v t u p t u o x a m 4 1 . 0 1 : x a m , 6 8 . 9 : n i m , 1 = r e t s a m _ r / n i a g _ r @ e g n a r e g a t l o v t u p t u o x a m 2 . 0 1 : x a m , 8 . 9 : n i m , 1 = r e t s a m _ r / n i a g _ r @ e g n a r t e s f f o t u p t u o 4 . 2 : x a m , 6 . 2 : n i m , 0 . 1 = r e t s a m _ r / t e s f f o _ r @ e g n a r t e s f f o t u p t u o 5 3 . 2 : x a m , 0 6 . 2 : n i m , 0 . 1 = r e t s a m _ r / t e s f f o _ r @ 5 8 2 0 0 0 . : p y t , o c p m e t n i a g 5 8 2 0 0 . : p y t , o c p m e t n i a g o c p m e t t e s f f o v 5 . 2 = t e s f f o v @ 2 7 : p y t , 0 = t e s f f o v @ v 5 . 2 = t e s f f o v @ v 5 . 3 = t e s f f o v @ o c p m e t t e s f f o 0 . 0 = r e t s a m _ r / t e s f f o _ r @ 0 1 1 : p y t , 5 . 0 = r e t s a m _ r / t e s f f o _ r 0 . 1 = r e t s a m _ r / t e s f f o _ r @ 2 . 1 = r e t s a m _ r / t e s f f o _ r @ 2 2s c i t s i r e t c a r a h c c de g n a r t e s f f o t u p t u o , 1 . 1 = r e t s a m _ r / t e s f f o _ r @ 5 9 . 2 : x a m , 5 0 . 3 : n i m e g n a r t e s f f o t u p t u o , 1 . 1 = r e t s a m _ r / t e s f f o _ r @ 9 . 2 : x a m , 0 1 . 3 : n i m 7 4 4 0 0 0 . : p y t , o c p m e t n i a g 2 1 0 0 . : p y t , o c p m e t n i a g o c p m e t t e s f f o v 5 . 2 = t e s f f o v @ 0 = t e s f f o v @ 2 3 1 + : p y t , v 0 . 3 = t e s f f o v @ v 5 . 3 = t e s f f o v @ o c p m e t t e s f f o 0 . 0 = r e t s a m _ r / t e s f f o _ r @ 5 . 0 = r e t s a m _ r / t e s f f o _ r @ 0 4 2 + : p y t , 1 . 1 = r e t a m _ r / t e s f f o _ r @ 2 . 1 = r e t s a m _ r / t e s f f o _ r @ 3 2s c i t s i r e t c a r a h c c de p u o r g e g n a r t n e r r u c t u p t u o x a m 2 3 . 3 : x a m , 4 1 . 3 : n i m , 5 . 2 6 = # _ n i a g _ r @ e c n a i l p m o c e g a t l o v t u p t u o 9 2 . 0 : n i m , a m 6 . 3 e g n a r t n e r r u c t u p t u o x a m 5 3 . 3 : x a m 9 0 . 3 : n i m , 5 . 2 6 = # _ n i a g _ r @ a m 2 . 3 @ : d d a : e c n a i l p m o c e g a t l o v t u p t u o 0 2 . 0 : n i m , a m 6 . 3 9 2 1 0 0 . : p y t , o c p m e t n i a g 1 2 0 0 . : p y t , o c p m e t n i a g f p u o r g e c n a i l p m o c e g a t l o v t u p t u o 2 : x a m , r o r r e y t i r a e n i l l a r g e t n i f p u o r g : e c n a i l p m o c e g a t l o v t u p t u o : d d a a m 5 1 . 3 5 2 . 0 : x a m , r o r r e y t i r a e n i l l a r g e t n i 9 2 1 0 0 . : p y t , o c p m e t n i a g 3 2 + : p y t , o c p m e t t e s f f o 7 5 0 0 . : p y t , o c p m e t n i a g 3 2 : p y t , o c p m e t t e s f f o 4 2s c i t s i r e t c a r a h c c d y l p p u s l a t i g i d , 2 y l p p u s g o l a n a e v i t i s o p 8 1 1 : x a m , 3 7 : n i m , y l p p u s r e w o p e v i t a g e n h f f f i d n a . . . : 4 e t o n 6 e t o n d d a 8 1 1 : x a m , 3 7 : n i m , y l p p u s r e w o p e v i t a g e n h f f f 1 d n a . . . : 4 e t o n 5 2s c i t s i r e t c a r a h c c ad d v d t a x a m f5 e t o n d d a
29 ? 2000 semtech corp. www .semtech.com high-performance products ?ate edge6420 revision history current revision: august 3, 2001 previous revision: june 28, 2001 # e g a pe m a n n o i t c e sn o i s i v e r s u o i v e r pn o i s i v e r t n e r r u c l l at e g r a ty r a n i m i l e r p 7 t u p t u o t n e r r u c c a d t e s f f o & w e i v r e v o : d d a s r e b m u n n o i t a u q e 8t e s f f o. . . t n e r r u c h c a e r o f t e s f f o e h t . . . t n e r r u c h c a e r o f t e s f f o l a c i p y t e h t 4 18 e l b a t2 1 , 1 1 s l e n n a h c a n 9 5 1 . 0 : n o i t u l o s e r 2 1 , 1 1 s l e n n a h c a n 9 5 1 : n o i t u l o s e r : e t e l e d 2 e t o n 5 1n o i t a m r o f n i n o i t a c i l p p a s i t i . . . : e c n e t n e s t s a l , s t u p t u o t n e r r u c . d e s u e b f p 0 0 1 t a h t d e d n e m m o c e r f n 1 o t f p 0 0 1 e g n a h c . d e s u e b f n 1 t a h t d e d n e m m o c e r s i t i . . . 6 1t n e i c i f f e o c e r u t a r e p m e t s c a d n o t c e f f e f o y r a m m u s a r o f h c e t m e s t c a t n o c " , h p a r g a r a p t s a l : d d a c t e v i r e d o t s n o i t a u q e t e s f f o c t d n a n i a g . 7 1e g a k c a p g b a 0 2 4 63 e t o n : e t e l e d " m m 0 3 . 0 f " t u b l l a 9 1 d e d n e m m o c e r s n o i t i d n o c g n i t a r e p o : e t e l e d 2 & 1 s e t o n : d d a s e t o n g n i n i a m e r r e b m u n e r , 4 d n a 1 s e t o n w e n : x a m , 0 0 0 0 5 . 2 : p y t , 5 7 4 . 2 : n i m , e g a t l o v e c n e r e f e r 5 2 5 . 2 s e u l a v x a m & n i m e t e l e d , 0 0 5 . 2 : p y t , e g a t l o v e c n e r e f e r 5 1 . 5 : x a m , 5 8 . 4 : n i m , y l p p u s r e w o p l a t i g i d 0 5 . 5 : x a m , 0 0 . 3 : n i m , y l p p u s r e w o p l a t i g i d , d b t : p y t , e g a k c a p f o e c n a t s i s e r l a m r e h t c ? : s t i n u r e t n e c - p o t t a d e r u s a e m ( e g a k c a p f o e c n a t s i s e r l a m r e h t w / c ? : s t i n u , 3 : p y t , ) e g a k c a p f o 0 2s g n i t a r x a m b as e g a t l o v t u p n i l a t i g i d : d d a s l o b m y s o t " e d o m _ t s e t , i d s " 1 2s c i t s i r e t c a r a h c c d2 1 0 0 . : p y t , o c p m e t n i a g 5 8 2 0 0 0 . : p y t , ) 6 , 3 s e t o n ( o c p m e t n i a g 4 2 3 + , 6 3 2 + , 0 , 0 0 2 : p y t , o c p m e t t e s f f o 1 3 2 + , 5 4 1 + , 2 7 , 8 8 2 : p y t , o c p m e t t e s f f o 2 2s c i t s i r e t c a r a h c c d : x a m , n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 2 , n o i t a r b i l a c t n i o p 2 h t i w r o r r e y t i r a e n i l l a r g e t n i 3 : x a m 5 1 0 0 . : p y t , o c p m e t n i a g 7 4 4 0 0 0 . : p y t , ) 6 , 3 s e t o n ( o c p m e t n i a g 5 2 3 + , d b t , 0 , 0 0 2 : p y t , o c p m e t t e s f f o 6 6 1 + , 2 3 1 + , 7 7 , 0 5 2 : p y t , o c p m e t t e s f f o 3 2s c i t s i r e t c a r a h c c de p u o r g 8 1 0 0 . : p y t , o c p m e t n i a g , d b t : p y t , o c p m e t t e s f f o f p u o r g o c p m e t n i a g d b t : p y t , o c p m e t t e s f f o e s p u o r g 9 2 1 0 0 . : p y t , ) 6 , 3 s e t o n ( o c p m e t n i a g 0 0 1 : p y t , o c p m e t t e s f f o f p u o r g ) 6 , 3 s e t o n ( o c p m e t n i a g 3 2 : p y t , o c p m e t t e s f f o 4 2s c i t s i r e t c r a h c c dd b t : x a m , d b t : p y t , y l p p u s l a t i g i d o i t a r n o i t c e j e r y l p p u s r e w o p d b t : p y t , z h m 1 d b t : p y t , z h k 0 0 5 d b t : p y t , z h k 0 0 1 0 1 : x a m , 2 : p y t , y l p p u s l a t i g i d o i t a r n o i t c e j e r y l p p u s r e w o p 5 6 : p y t , z h m 5 5 4 : p y t , z h m 1 0 5 : p y t , z h k 0 0 1 : d d a y t i v i t i s n e s c d y l p p u s r e w o p 4 2 s c i t s i r e t c r a h c c d ) s e t o n ( v 0 0 0 0 5 . 2 = f e r vv 0 5 . 2 = f e r v 5 2s c i t s i r e t c a r a h c c a) 4 e t o n ( v 3 . 3 = d d v d t a x a m f ) 1 e t o n ( v 0 . 5 = d d v d t a x a m f ) 1 e t o n ( v 0 3 . v 3 . 3 = d d v d t a x a m f ) 4 e t o n ( v 0 5 . v 0 . 5 = d d v d t a x a m f v 0 1 o t 0 , p e t s e l a c s l l u f , d b t : x a m , f n 0 0 1 : d a o l , d b t : x a m , f n 0 1 : d a o l s m : s t i n u s : s t i n u , f n 0 0 1 : d a o l , v 7 1 o t 0 , p e t s e l a c s l l u f v 0 1 , p e t s e l a c s l l u f : s t i n u , 0 0 7 : x a m , f n 0 0 1 : d a o l , 0 7 : x a m , f n 0 1 : d a o l s s m : s t i n u , f n 0 0 1 : d a o l , v 7 1 , p e t s e l a c s l l u f y t i v i t i s n e s y l p p u s r e w o p : e t e l e d . . . y l n o z h m 3 3 t a d e t s e t : 4 e t o n e c n e t n e s t s a l e t e l e d ; y l n o z h m 5 5 t a d e t s e t : 4 e t o n

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